The present invention relates to a digital signal delay circuit which includes a plurality of delay sections each delaying a digital input signal independently for a desired time.
For example, digital signals from a digital pattern generater are applied to a digital circuit to be tested. In this instance, it is convenient to change phase of each bit of the parallel digital signals from the pattern generater independently, i.e., delay each bit of the digital signals independently for a desired time in accordance with characteristics of the digital circuit under test. Even if the digital signal is but a single digit, it may be used to produce a multiple-digit output signal by digit input by delaying the single signal for different times. For this purpose, a digital signal delay circuit having a plurality of digital sections is needed.
In a conventional digital signal delay circuit disclosed in U.S. Pat. No. 4,458,165, each of the delay sections includes variable delay means. This variable delay means comprises a plurality of delay devices (e.g. delay lines, lumped parameter delay lines, active devices, such as buffer amplifiers, logic gates, etc.) connected in series for delaying an input digital signal, and selection means for selecting one of the output signals from the delay devices for controlling the delay time.
Since the conventional circuit needs a plurality of delay devices and a selection means for each delay section, as the number of delay sections increases, the number of the delay devices increases also. Thus, the circuit becomes expensive and complex. It is necessary that the delay times of the delay devices in the delay sections are equal to each other for matching the delay characterictics of the delay sections. However, it is difficult to achieve a match in the delay characteristics of many delay devices.